1. Field of the Invention
This invention relates to multichip electronic packaging techniques. In particular, this invention relates to packaging techniques which utilize interconnected semiconductor chips on substrates within hermetically sealed packages.
2. Description of the Prior Art
Conventional multichip electronic assemblies provide packaging and integration of semiconductor devices, typically silicon chip integrated circuits (IC's), interconnected on a ceramic substrate in a hermetically sealed enclosure. Although widely used, the heat transfer mismatch between the silicon chips and the ceramic substrates limits chip density and operating life. Such conventional multichip assemblies are often packaged in hermetically sealed ceramic and/or metal cans which result in additional thermal mismatch between the substrate and the package.
Silicon substrates have been used in special purpose electronic packaging techniques such as wafer scale integration. In that technique, each silicon wafer is designed as a special purpose circuit to be packaged as a single unit rather than as a series of identical individual circuits designed to be separated into semiconductor chips and separately packaged during manufacturing. Wafer scale integration (WSI) provides very high packaging densities but is a time consuming and extremely expensive process because it requires new designs for each circuit or circuit change. This is a particular drawback for use with circuits which will not be manufactured in large quantities, such as circuits used for prototyping or other short production run activities. In addition, WSI requires circuit and component redundancy in order to provide for circumvention of defective components during the manufacturing process.
Silicon substrates may be used with chip-to-substrate interconnection techniques such as tape automated bonding, TAB, or flip chips in Which semiconductor chips specially configured with interconnect extensions are mounted or solder bumped and connected on matching portions of a silicon substrate. The use of silicon substrates with flip chips was reported by AT&T Bell Laboratories, at the 1987 IEEE ISSCC conference, to provide improved performance and increased packaging density.
A cost effective, high performance, high density multichip silicon substrate assembly technique, using TAB and/or more conventional interconnect techniques, is not currently available. Conventional approaches have not provided a suitable alternative to hermetic sealed multichip assembly integral with a thermally matched substrate. In addition conventional approaches have not been effective in extending the high density interconnect monolithic silicon technology to the input-output or I/O leads of the packaged assembly.